An integrated circuit 10 of a known design having a plurality of processing modules, is shown schematically in FIG. 1. In FIG. 1, for simplicity only three modules 3, 5, 7 are shown. Each module 3, 5, 7 has inputs labelled i1, i2, . . . and outputs labelled o1, o2, . . . . The integrated circuit has a plurality of input pins 9 (for simplicity only two such inputs 9 is shown), which receive in put signals which are transmitted to one of more of the modules 3, 5, 7, and also output pins 11 (for simplicity only two such output pins 11 are shown). Furthermore, the modules 3, 5, 7 are interconnected, such that signals generated at some outputs of some modules are transmitted to be inputs of other modules (e.g. the output o2 of module 5 is the input i2 of module 7). In other words, a given module 3, 5, 7 may have any number of two different sorts of input pins: input pins which input signals directly received by the integrated circuit and input pins which receive the outputs of other pins.
Due to problems in the production process of the integrated circuits, individual modules 3, 5, 7 may be faulty, and therefore integrated circuits should be tested to identify if the integrated circuits are faulty, and in what respect. Typically, an integrated circuit 1 is tested by sequentially supplying predefined sets of signals to the input pins 9 of the integrated circuit, and observing the signals output from the output pins 11 of the integrated circuit. The term “scan chain” is used to refer to the path from the input pins, through one or more modules 3, 5, 7 being tested at any given time, to the output pins.
A problem with such an approach is that it can be a complex operation to adequately test all the modules 3, 5, 7 of the chip, because of interactions between the modules 3, 5, 7. The problem is particularly acute if the number of input pins 9 to the integrated circuit (only two in the simplified example of FIG. 1) and/or the number of output pins 11 of the integrated circuit (again, two in the example of FIG. 1), are less than the total number of inputs to all the modules 3, 5, 7 (eight in the simplified example of FIG. 1). In this case, it may be impossible in principle to identify which of the modules 3, 5, 7 is at fault and what type of fault it is.
The reason for this is that the scan chains are entangled, since one module being tested will influence other modules. For example, if a given first module 3 is faulty such that it generates an erroneous output signal to a second module 5, it can be impossible to identify whether the problem is with the first module 3 or the second module 5. If, during the testing procedure all but one of the modules are disabled completely (so that only one scan chain is enabled) then the ability of that module to send/receive signals to/from other modules is not checked at all.